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Top-Down Digital VLSI Design,

Edition 1 From Architectures to Gate-Level Circuits and FPGAs

Editors: By Hubert Kaeslin

Publication Date: 04 Dec 2014

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Top-Down VLSI Design: From Architectures to Gate-Level Circuits and FPGAs represents a unique approach to learning digital design. Developed from more than 20 years teaching circuit design, Doctor Kaeslin’s approach follows the natural VLSI design flow and makes circuit design accessible for professionals with a background in systems engineering or digital signal processing. It begins with hardware architecture and promotes a system-level view, first considering the type of intended application and letting that guide your design choices.

Doctor Kaeslin presents modern considerations for handling circuit complexity, throughput, and energy efficiency while preserving functionality. The book focuses on application-specific integrated circuits (ASICs), which along with FPGAs are increasingly used to develop products with applications in telecommunications, IT security, biomedical, automotive, and computer vision industries. Topics include field-programmable logic, algorithms, verification, modeling hardware, synchronous clocking, and more.

Key Features

Demonstrates a top-down approach to digital VLSI design.
Provides a systematic overview of architecture optimization techniques.
Features a chapter on field-programmable logic devices, their technologies and architectures.
Includes checklists, hints, and warnings for various design situations.
Emphasizes design flows that do not overlook important action items and which include alternative options when planning the development of microelectronic circuits.

About the author

By Hubert Kaeslin, Head of the Micro-electronics Design Center of ETH, Zurich, Switzerland

Preface
- Why this book?
- Highlights
- Notes to instructors
Acknowledgments
Chapter 1: Introduction to Microelectronics
- Abstract
- 1.1 Economic impact
- 1.2 Microelectronics viewed from different perspectives
- 1.3 The VLSI design flow
- 1.4 Problems
- 1.5 Appendix I: a brief glossary of logic families
- 1.6 Appendix II: an illustrated glossary of circuit-related terms
Chapter 2: Field-Programmable Logic
- Abstract
- 2.1 General idea
- 2.2 Configuration technologies
- 2.3 Organization of hardware resources
- 2.4 Commercial aspects
- 2.5 Extensions of the basic idea
- 2.6 The FPL design flow
- 2.7 Conclusions
Chapter 3: From Algorithms to Architectures
- Abstract
- 3.1 The goals of architecture design
- 3.2 The architectural solution space
- 3.3 Dedicated vlsi architectures and how to design them
- 3.4 Equivalence transforms for combinational computations
- 3.5 Options for temporary storage of data
- 3.6 Equivalence transforms for non-recursive computations
- 3.7 Equivalence transforms for recursive computations
- 3.8 Generalizations of the transform approach
- 3.9 Conclusions
- 3.10 Problems
- 3.11 Appendix I: A brief glossary of algebraic structures
- 3.12 Appendix II: Area and delay figures of VLSI subfunctions
Chapter 4: Circuit Modeling with Hardware Description Languages
- Abstract
- 4.1 Motivation and background
- 4.2 Key concepts and constructs of VHDL
- 4.2.3 A discrete replacement for electrical signals
- 4.2.4 An event-driven scheme of execution
- 4.2.5 Facilities for model parametrization
- 4.2.6 Concepts borrowed from programming languages
- 4.3 Key concepts and constructs of systemverilog
- 4.3.6 Concepts borrowed from programming languages
- 4.4 Automatic circuit synthesis from hdl models
- 4.5 Conclusions
- 4.6 Problems
- 4.7 Appendix I: VHDL and systemverilog side by side
- 4.8 Appendix II: VHDL extensions and standards
Chapter 5: Functional Verification
- Abstract
- 5.1 Goals of design verification
- 5.2 How to establish valid functional specifications
- 5.3 Preparing effective simulation and test vectors
- 5.4 Consistency and efficiency considerations
- 5.5 Testbench coding and hdl simulation
- 5.6 Conclusions
- 5.7 Problems
- 5.8 Appendix I: Formal approaches to functional verification
- 5.9 Appendix II: Deriving a coherent schedule for simulation and test
Chapter 6: The Case For Synchronous Design
- Abstract
- 6.1 Introduction
- 6.2 The grand alternatives for regulating state changes
- 6.3 Why a rigorous approach to clocking is essential in VLSI
- 6.4 The dos and donts of synchronous circuit design
- 6.5 Conclusions
- 6.6 Problems
- 6.7 Appendix: on identifying signals
Chapter 7: Clocking of Synchronous Circuits
- Abstract
- 7.1 What is the difficulty with clock distribution?
- 7.2 How much skew and jitter does a circuit tolerate?
- 7.3 How to keep clock skew within tight bounds
- 7.4 How to achieve friendly input/output timing
- 7.5 How to implement clock gating properly
- 7.6 Summary
- 7.7 Problems
Chapter 8: Acquisition of Asynchronous Data
- Abstract
- 8.1 Motivation
- 8.2 Data consistency in vectored acquisition
- 8.3 Data consistency in scalar acquisition
- 8.4 Marginal triggering and metastability
- 8.5 Summary
- 8.6 Problems
Appendix A: Elementary Digital Electronics
- A.1 Introduction
- A.2 Theoretical background of combinational logic
- A.3 Circuit alternatives for implementing combinational logic
- A.4 Bistables and other memory circuits
- A.5 Transient behavior of logic circuits
- A.6 Timing quantities
- A.7 Basic microprocessor input/output transfer protocols
- A.8 Summary
Appendix B: Finite State Machines
- B.1 Abstract automata
- B.2 Practical aspects and implementation issues
- B.3 Summary
Appendix C: Symbols and Constants
- C.1 Abbreviations
- C.2 Mathematical symbols
- C.3 Physical and material constants
Bibliography
Index

ISBN: 9780128007303

Page Count: 598

Retail Price (USD) :

Harris, Digital Design and Computer Architecture 2e, MK, 9780123944245, 2012, $89.95
Wilson, The Circuit Designer's Companion 3e, Newnes, 9780080971384, 2012, $69.95
Ashenden, Digital Design: An Embedded Systems Approach using Verilog, MK, 9780123695277, 2007, $105
Ashenden, Digital Design: An Embedded Systems Approach using VHDL, MK, 9780123695284, 2007, $105

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